This invention relates generally to high electron mobility transistor (HEMT) structures and, more particularly, to HEMTs using indium phosphide (InP) and related materials. A HEMT is a type of field effect transistor (FET) in which current flow between two terminals, referred to as the source and drain terminals, is controlled by a voltage applied to a gate terminal. HEMTs are widely used in a variety of applications, but particularly as low noise amplifiers operating at microwave and millimeter wave frequencies. HEMTs may be implemented as discrete transistors or in integrated circuits, such as microwave monolithic integrated circuits (MMICs) in space, military and commercial applications.
The present invention is particularly concerned with a known disadvantage of the InP HEMT, which includes, for example, a channel layer of indium gallium arsenide (InGaAs) and a barrier layer of indium aluminum arsenide (InAlAs) formed over an InP substrate. For brevity, this structure will be referred to in this description as the InP HEMT or the 0.1 μm InP HEMT, where the designation 0.1 μm refers to the minimum feature size or geometry of the structure. An important issue for users of InP HEMTs is long term reliability, because in many applications the devices are used in space or in similar environments in which repair and replacement are not practical alternatives.
Superior microwave and millimeter wave performance of InP HEMT MMICs for space and military applications has been demonstrated and discussed in the technical literature. Moreover, this superior performance has been demonstrated for circuits operating over a range of frequencies from, for example, 44 GHz (gigahertz) to 183 GHz or higher. To warrant the reliability of InP HEMTs during lifetime operation, it is essential to demonstrate their high reliability performance when subjected to an elevated temperature lifetest. Testing at an elevated temperature for relatively short periods is an acceptable substitute for testing at normal operating temperatures for much longer periods. Accordingly, since at least as early as 1993 the elevated temperature reliability of InP HEMTs, either discrete transistors or MMICs, has been extensively investigated by researchers in various industries. As a result, high reliability performance has been demonstrated for 0.07 μm, 0.1 μm InP HEMTs, and for the metamorphic HEMT (MHEMT). These investigations together demonstrate the maturity of the InP HEMT and MHEMT technologies and the degree to which these technologies are ready for space, military and commercial applications. For example, high performance and high reliability InP HEMT low noise amplifiers operating at Q-band (30-50 GHz) for phased-array applications have been demonstrated by some of the present inventors, as described in a recent publication. (R. Grundbacher, Y. C. Chou, R. Lai, K. Ip, S. Kam, M. Barsky, G. Hayashibara, D. Leung, D. Eng, R. Tsai, M. Nishimoto, T. Block, P. H. Liu and A. Oki, “High Performance and High Reliability InP HEMT Low Noise Amplifiers for Phased-Array Applications,” Technical Digest of International Microwave Symposium, pp. 157-160, 2004.)
Although supreme reliability performance of InP HEMTs has been demonstrated in industry, it has been found that the reliability performance varies from company to company. The variations of reliability performance have been attributed to several different degradation mechanisms, including fluorine contamination, ohmic contact degradation, gate metal stacks, layer structure, bias dependence, variation of gate recess depth, and gate metal sinking. It appears, therefore, that the reliability performance and the degradation mechanisms strongly depend on the process techniques employed in a particular InP HEMT technology. Accordingly, it is important to identify the degradation origin of InP HEMTs on the various established process techniques in order to further improve the reliability performance. Ideally, if the origin of InP HEMT performance degradation can be reliably identified there is a significant need to provide an InP HEMT structure that improves the reliability performance of InP HEMTs, regardless of their field of application. The present invention is directed to these ends.